1. Field of the Invention
The present invention generally relates to dynamic frequency divider circuits, and particularly to a dynamic frequency divider circuit using an inverter in it. The present invention has particular applicability to a phase-locked loop (PLL) circuit using a dynamic frequency divider operable in the microwave band.
2. Description of the Background Art
Generally, frequency dividers are widely used in various electric circuits for changing frequency of provided input signals into ones with lower frequency. For example, in phase-locked loop (hereinafter referred to as "PLL") circuits, frequency dividers are often used. PLL circuits including frequency dividers are also often used in communication apparatus and measuring apparatus operable in the microwave band. The PLL circuit will be briefly described as one example of application of frequency dividers.
FIG. 1 is a block diagram of a PLL circuit. Referring to FIG. 1, the PLL circuit includes a reference oscillator 31 for producing reference signals, a phase comparator 32, a low-pass filter (LPF) 33, a voltage control oscillator (VCO) 34, N stages of a clock signal generating circuit 35 and a dynamic frequency divider (or prescaler) 36, and a programmable frequency divider 37.
In operation, reference oscillator 31 produces a reference signal S10 having a frequency f.sub.in, and provides it to phase comparator 32. Phase comparator 32 compares reference signal S10 and a signal S15 provided from programmable frequency divider 37 to produce a phase error signal S11. Phase error signal S11 is supplied to VCO 34 through LPF 33. An output signal S13 provided from VCO 34 has a frequency f.sub.out, which is provided as an output signal of the PLL circuit, and also fed back to phase comparator 32 through circuits 35, 36 and 37.
Clock signal generating circuit 35 receives an output signal S13 from VCO 34, generates clock signals .phi.1' and .phi.1' inverted with respect to each other, and provides them to dynamic frequency divider 36. The dynamic frequency divider 36 and the clock signal generating circuit 35 are cascaded for N stages. A single frequency divider circuit reduces the frequency of a provided clock signal to half. Accordingly, N stages of dynamic frequency dividers 36 provide a clock signal S14 having frequency (1/2) .sup.N .multidot.f.sub.out as an output. Programmable frequency divider 37 divides the frequency of the supplied clock signal S14 to 1/M according to a program stored in advance. Accordingly, a clock signal S15 having a frequency (1/2).sup.N /M.multidot.f.sub.out is provided as an output from programmable frequency divider 37, which is supplied to phase comparator 32. Accordingly, the relationship between frequencies of two signals S10 and S15 supplied to phase comparator 32 is expressed as the following expression; EQU f.sub.in =(1/2).sup.N /M.multidot.f.sub.out ( 1).
For example, when an output signal S13 of f.sub.out =15 GHz is provided as an output from the PLL circuit, the dynamic frequency divider 36 is formed of 1/2 frequency divider circuits of three stages (N=3) and the ratio of frequency division of programmable frequency divider 37 is set to 64 (M=64). Accordingly, the frequency of an output signal S14 of dynamic frequency divider 36 is 2.5 GHz and the frequency of an output signal S15 of programmable frequency divider 37 is 29.297 MHz. Accordingly, the reference oscillator 31 is required to generate a reference signal S10 of 29.297 MHz.
The PLL circuit includes dynamic frequency divider 36 having frequency divider circuits cascaded into N stages as described above, but one dynamic frequency divider circuit of a single stage will be described in the following description.
FIG. 2 is a circuit diagram of a dynamic frequency divider circuit 3a of a single stage. A circuit similar to the frequency divider circuit can be found in a thesis entitled "15 GHz GaAs dynamic prescaler" (Denki Tsushin Gakkai Ronbunshu, ED88-129, 1988).
Referring to FIG. 2, the frequency divider circuit 3a includes an inverter 1a formed of a buffered FET logic (BFL) circuit, depletion type MESFETs 25 and 26 which alternately turn on in response to input signals .phi.1' and .phi.1', and a buffer 2 connected between MESFETs 25 and 26 for current amplification. One electrode of MESFET 26 is connected to an input of inverter 1a. In the following description, each MESFET 25 and 26 is referred to as "a transmission gate". A signal .phi.2 having a frequency which is half of that of an input signal .phi.1' is provided as an output through a common connection node of buffer 2 and MESFET 26.
Next, operation of the dynamic frequency divider circuit 3a shown in FIG. 2 will be described. First, it is assumed that a signal S1 of a low level is applied to inverter 1a, and a signal .phi.1' of a low level and a signal .phi.1' of a high level are applied to transmission gates 25 and 26. Accordingly, transmission gate 25 turns off and transmission gate 26 turns on. Buffer 2 provides an output signal .phi.2 of a low level.
Next, when input signals .phi.1' and .phi.1' turn into a high level and a low level, respectively, transmission gate 25 turns on and transmission gate 26 turns off. A signal S2 of a high level outputted from inverter 1a is provided to buffer 2 through transmission gate 25. Buffer 2 current-amplifies the provided signal S3 and holds the amplified signal. Accordingly, the level of the output signal .phi.2 of buffer 2 changes from a low level to a high level. Transmission gate 26 is then OFF, so that a signal of a high level is not transmitted to inverter 1a.
Furthermore, when an input signal .phi.1' of a low level and an input signal .phi.1' of a high level are provided, transmission gates 25 and 26 turn off and on, respectively. Accordingly, a high level signal outputted from buffer 2 is applied to inverter 1a through transmission gate 26, and an output signal S2 falls to a low level after a delay time by inverter 1a. Then, since transmission gate 25 has been already turned off, an output signal S2 of a low level is not transmitted to buffer 2. Accordingly, an output signal .phi.2 is maintained at the high level.
Operation in the case where an input signal .phi.1 changes in the order of "low level"--"high level"--"low level" has been described in the above description, and the dynamic frequency divider circuit 3a returns to the condition assumed first by repeating the signal cycle of an input signal .phi.1' once again. This means that frequency divider circuit 3a performs 1/2 frequency dividing operation.
In the dynamic frequency divider circuit 3a shown in FIG. 2, the holding time of signal charge is determined with the gate capacitance and the wiring capacitance of a circuit connected to an output side of each transmission gate 25 and 26 and the leakage conductance thereof. In other words, the frequency divider circuit 3a performs "dynamic operation", and the lowest limit frequency at which the frequency divider circuit 3a is operable is determined on the basis of the length of the time in which the signal charge can be held.
Next, a problem which occurs in the frequency divider circuit 3a shown in FIG. 2 will be described. As seen from the above description, an output signal S2 of inverter 1a returns to an input of inverter 1a via a loop formed in frequency divider circuit 3a. That is to say, output signal S2 is returned to inverter 1a through transmission gate 25, buffer 2 and transmission gate 26, so that the direct current (hereinafter referred to as "DC") voltage of the returned signal S1 is shifted to the lower direction. This is because the gains of buffer 2 formed of a source follower circuit and transmission gates 25 and 26 are generally set 1.0 or lower. Accordingly, the DC voltage level of the signal S1 returned to inverter 1a, or the voltage level at the center of the swing of signal S1 becomes lower than the threshold voltage level of inverter 1a. That is, as shown in FIG. 9, since the center voltage level Vcel of the swing of the input signal S1 becomes lower than the threshold voltage level Vti of inverter 1a, inverter 1a provides the signal S2 shown in FIG. 9 as an output. The output signal S2 does not have a duty cycle of 50% as seen from FIG. 9. In other words, a change in the duty cycle is caused by inverter 1a. As a result, a malfunction is caused in frequency divider circuit 3a. As a result, for example, the PLL circuit shown in FIG. 1 does not operate normally.
In addition to the above-stated problem, it is pointed out that a problem as described below is caused in the frequency divider circuit 3a shown in FIG. 2. FIG. 3 is a circuit diagram of inverter 1a shown in FIG. 2. Inverter 1a is formed of a buffered FET logic (BFL) circuit, which includes MESFETs operating in the depletion mode. The MESFETs have negative threshold voltage Vth. MESFETs 25 and 26 in the frequency divider circuit 3a shown in FIG. 2 also have threshold voltage Vth of the same value. Accordingly, the voltage level of a high frequency signal transmitted through transmission gate 25 or 26 is shifted by the voltage value of the threshold voltage Vth. Accordingly, the DC voltage level of the input signal .phi.1' supplied to the gate of transmission gate 25 should be set to be lower than the DC voltage level of an input signal S2 of inverter 1a by .vertline.Vth.vertline.. Similarly, the clock signal .phi.1' supplied to the gate of transmission gate 26 should be also set to be lower than the DC voltage level of the output signal .phi.2 by .vertline.Vth.vertline..
FIG. 4 is a waveform diagram of an input/output signals of the dynamic frequency divider shown in FIG. 2. In other words, in order to provide an output signal .phi.2 which swings about the DC voltage level of 0 volt, it is required to supply an input signal .phi.1' which swings about that DC voltage level lower than the DC voltage level by about .vertline.Vth.vertline.. That is to say, in the example shown in FIG. 4, since the frequency of input signal .phi.1' is 5 GHz and Vth =-0.8 volt, an input signal .phi.1' which swings with a center DC voltage level of -0.8 volt is supplied. As a DC voltage level difference is needed between the input signal .phi.1' and the output signal .phi.2, it is not preferable in view of matching of input/output signals to connect frequency divider circuits over a plurality of stages. For example, in the PLL circuit (FIG. 1) having frequency divider circuit 36 cascaded for N stages, a malfunction may occur.